1. Field of the Invention
The present invention relates to high-speed circuits for converting Emitter-Coupled-Logic (ECL) level signals into corresponding Bipolar-CMOS (BICMOS) level signals and more particularly to a method and apparatus for high-speed level conversion employing a capacitively coupled pull-down circuit connected across an output load. The invention further relates to a method and apparatus for generating high speed trailing edge transitions in the output of an ECL circuit which employ a clamped bootstrap driver having an input connected to one output of a differential current switching device through a boost capacitor.
2. Background of the Art
Circuitry used in advanced integrated circuits often employs several different families or types of logic circuits to take advantage of specific operating features or parameters. That is, ECL, TTL, BICMOS, and other types of logic circuits each have inherent operating features in terms of input impedance, power dissipation, voltage levels required, output impedance, etc. that make them well suited to particular switching or logic operations. Therefore, circuits such as ECL logic elements, which are well suited as high speed switching components with low input impedances, are often used in conjunction with TTL circuit elements which drive high current loads, or BICMOS elements which dissipate very little power and provide excellent output impedances.
However, the different logic types or families operate at incompatible signal levels, requiring signal level converters to transfer signals between and through an overall circuit. Therefore, it is necessary to be able to efficiently convert from one signal level, say ECL, to another level, say BICMOS, at high signal transfer rates to take full advantage of the characteristics of the separate circuit elements. Exemplary circuits for accomplishing these type of conversions are shown in U.S. Pat. Nos. 4,453,095, 4,347,446, 4,629,913, and 3,766,406.
A major problem in converting between different types of logic or signal levels is the fact that successive circuit elements or stages often act as large capacitive loads for the converter, especially with BICMOS and TTL circuit elements. This large capacitive load produces signal propagation delays and effects the decay times between signal level transitions. The trailing edges of digital pulse signals become sloped and extended over a longer period instead of having a desired sharp (short period) transition. This causes general signal distortion and processing problems in later stages.
In an attempt to solve the transition problems a pull-down or boost circuit can be employed to assist the converter in removing the charge stored in the large capacitance of the load circuit. One type of pull-down element is shown in U.S. Pat. Nos. 4,629,913 and 3,766,406, where a pull-down transistor is placed across the output load in order to pass current from the load to the lowest circuit potential. However, the pull-down transistors in these inventions continue to draw the pull-down current even after the output falls to a low state. The power dissipated by this extra current is very undesirable.
In U.S. Pat. No. 4,347,446, the pull-down transistor is referenced to an independent voltage source which is controlled to bias the pull-down transistor in the off state when the output signal is in low state. While this decreases the current requirement during the low state period it increases the complexity of the overall circuit and requires a third, programmable, high-current voltage source. This adds complexity and undesirable switching speed complications. This circuit also is incapable of generating both true and complementary outputs simultaneously, which is very important in modern VLSI.
Other techniques have included the addition of resistors and diodes to act as current paths during signal transitions to reduce the voltage inherently stored by the capacitance of current from the output load. However, all of these techniques have proven unsatisfactory in terms of power consumption or undue complexity.
What is needed is a method and apparatus for improving the transition behavior of logic level converters which requires minimum circuit alteration or structure and is very efficient at high signal rates.
More generally, capacitative effects reduce the potential speed at which ECL circuitry can operate, preventing utilization of the full bandwidth capacity of the circuitry. As processing requirements push toward picosecond switching times, every measure must be taken to overcome the hindrances to ECL circuit operation.